In the prior art, every two horizontally adjacent sub pixels in a half source driving (HSD) pixel array share a data line, as shown in FIG. 1. For example, a second sub pixel and a third sub pixel in a first pixel unit row share a data line D2, and a fourth sub pixel and a fifth sub pixel therein share a data line D3. In this case, the number of data lines can be reduced by half as compared with a traditional liquid crystal drive pixel array. Adjacent sub pixels in a same row are connected with different gate lines, and every other sub pixel therein is connected with the same gate line. For example, the second sub pixel and the fourth sub pixel in the first pixel unit row are connected with a gate line G1, and the third sub pixel and the fifth sub pixel therein are connected with a gate line G2. In this case, two longitudinally adjacent sub pixels are connected with different gate lines. However, the above arrangements cause the number of gate lines to double as compared with the traditional drive pixel array.
Take a two-dot inversion drive mode of a data signal as an example, in an HSD pixel array, the corresponding situation between the data signal and a drive signal of the gate line is as shown in FIG. 2. Because the number of gate lines doubles, the scanning time distributed to each gate line is reduced, whereby the time for charging the sub pixels is reduced. As shown in FIG. 3, a high level signal of the data line usually charges two columns of sub pixels on both sides of the data line simultaneously. In the meantime, because the sub pixels in the two columns are respectively connected with different gate lines, the two columns of sub pixels are driven in a chronological order. In other words, the high level signal charges an odd numbered column of sub pixels during the first half time, and an even numbered column of sub pixels during the latter half time.
The inventor found out that due to certain resistance of the data line, delay distortion would occur to the waveform of the data signal during transmission, causing distortion of data signal of both even numbered and odd numbered data lines. Specifically, as shown in FIG. 2, the ideal waveform of the data signal is a rectangular wave (dashed line as shown in FIG. 2). However, due to the influence of the delay distortion, the data signal rises slowly for the first half time of the waveform, and reaches a pre-determined voltage value until the latter half time of the same waveform. In this case, the charge volume of sub pixels driven by odd numbered gate lines during the first half time of the waveform is lower than that of the sub pixels driven by the odd numbered gate lines during the latter half time of the waveform. Consequently, the sub pixels driven first are undercharged, thus have relatively low brightness. By contrast, sub pixels driven later are better charged, thus have relatively high brightness. In view of FIGS. 1 and 2, sub pixels driven by even numbered gate lines are in the same column, and sub pixels driven by odd numbered gate lines are in the same column. As a result, bright lines and dark lines would appear on the entire HSD pixel array.
Based on the foregoing, a display panel which can eliminate the defect of bright lines and dark lines of the HSD pixel array is needed.